TY  - BOOK
AU  - Bhasker,Jayaram
TI  - Verilog HDL synthesis: a practical primer 
SN  - 0965039153
AV  - TK7885.7 .B5284 1998
U1  - 621.39/2 21
PY  - 1998///
CY  - Hyderabad
PB  - BS Publication.
KW  - Verilog (Computer hardware description language)
KW  - Logic design
KW  - Data processing
N1  - Includes bibliographical references (p. 209) and index
ER  -