| 000 -LEADER |
|---|
| fixed length control field |
01441cam a2200349 a 4500 |
| 001 - CONTROL NUMBER |
|---|
| control field |
2583231 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
19990415104455.1 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
960508s1996 alua 001 0 eng d |
| 010 ## - LIBRARY OF CONGRESS CONTROL NUMBER |
|---|
| LC control number |
96084641 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
0965193438 |
| 035 ## - SYSTEM CONTROL NUMBER |
|---|
| System control number |
(OCoLC)35553898 |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
JFM |
| Transcribing agency |
JFM |
| Modifying agency |
DLC |
| 042 ## - AUTHENTICATION CODE |
|---|
| Authentication code |
lccopycat |
| 050 00 - LIBRARY OF CONGRESS CALL NUMBER |
|---|
| Classification number |
TK7874.6 |
| Item number |
.S62 1996 |
| 082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER |
|---|
| Classification number |
621.39/5 |
| Edition number |
21 |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Smith, Douglas J. |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
HDL chip design : |
| Remainder of title |
a practical guide for designing, synthesizing, and simulating ASICs and FPGAs using VHDL or Verilog / |
| Statement of responsibility, etc |
Douglas J. Smith. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Madison, AL : |
| Name of publisher, distributor, etc |
Doone Publications, |
| Date of publication, distribution, etc |
c1996. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xvi, 448 p. : |
| Other physical details |
ill. ; |
| Dimensions |
29 cm. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
Includes index. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Application specific integrated circuits |
| General subdivision |
Computer-aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Field programmable gate arrays |
| General subdivision |
Computer-aided design. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Logic design |
| General subdivision |
Data processing. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
VHDL (Computer hardware description language) |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Verilog (Computer hardware description language) |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) |
|---|
| a |
7 |
| b |
cbc |
| c |
copycat |
| d |
2 |
| e |
opcn |
| f |
19 |
| g |
y-gencatlg |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Koha item type |
Books |